The present invention generally relates to an integrated circuit structure, and more particularly to a structure for forming integrated circuit channel capacitors suitable for a high frequency operation.
A variety of integrated circuit capacitor structures have been developed over the years. Very often the structures which create the capacitors are intimately related to the integrated circuit fabrication process, to the effect that capacitor structures vary considerably. For example, U.S. Pat. No. 4,419,812 teaches a capacitor structure employing two parallel plate layers of consecutively formed polysilicon, requiring a two polysilicon layer fabrication process. Functional constraints are also common for prior art configurations. For example, U.S. Pat. Nos. 3,860,945 teaches the structure of an integrated circuit capacitor produced by a reverse biased p-n junction in a refined epitaxial configuration. The structure of an integrated circuit capacitor formed between a dielectrically isolated electrode as one terminal and a heavily doped substrate region as the second terminal is described in U.S. Pat. No. 4,156,249. In that case, the effective area of the capacitor plate formed by the heavily doped substrate electrode is varied by laterally disposed and dimensionally modifiable depletion regions.
In the presence of such prior art, there exists a need for an integrated circuit capacitor which is able to utilize the minimum design rules of field effect transistor gate structures and the minimum design rules of semiconductor diffusions to create low resistivity capacitor regions suitable for high frequency applications.